Semiconductor start-up XCENA reports closing a $135 million Series B financing. That brings its total round of funding to $185 million and wins it a post-money valuation of $570 million. And, in a remarkable reversal for hardware, it demonstrates a significant transformation in the hardware. The chief limiting factor for generative AI quality is rapidly shifting from computing power to memory.
The round was co-led by major South Korean venture capital firms Atinum Investment and IMM Investment. It was well supported by a broad syndicate of new and existing institutional investors across Asia, including SBI Investment, Mirae Asset Capital, Corstone Asia, Kiwoom Investment and the Korea Development Bank.
Challenging the Von Neumann Bottleneck
Generally, when dealing with a computer, the architecture in question is that of having data stored in one place, the memory, while it is worked on elsewhere, the CPU or the GPU. For most applications, this physical separation is not a problem, because the distance is just insignificant. For large language models, however, data needs to be moved all the time to increase context window sizes, perform data analyses and generate tokens. This bottleneck of constant data circulating comes at a cost. Latency increases, energy expenditure will become very high, and overall efficiency can only be scaled to a certain degree; this is known as the von Neumann bottleneck or memory wall.
Source: XCENA
XCENA addresses it by means of memory-centric computing, an engineering field that integrates large memory arrays much bigger than typical processor caches right with the computational resources. Instead of moving data back and forth across long, slow links, as conventional processor-accelerator systems do, XCENA performs computation where the data sits.
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The MX1 Architecture and CXL Standard
The cornerstone of XCENA’s strategy is its flagship MX1 computational memory solution. Using the open standard Compute Express Link (CXL 3.x standard), MX1 can be directly linked to host processors via high-speed cache-coherent lanes. Besides, the device embeds thousands of power-efficient, proprietary RISC-V processing cores and vector engines directly with the pooled DDR5 memory.
In operation, the MX1 takes many of the most intensive, data-centric tasks in the system, such as preprocessing, key-value (KV) cache management, and data caching inside the memory module itself. By removing the data design from the primary server chips, XCENA offers an incredible reduction in infrastructure footprint. Preliminary metrics show that under certain computationally intensive workloads, hardware with no more than a single line of MX1s can produce results that would otherwise have used many expensive real servers.
To simplify adoption, the startup is also packaging its hardware with a full-stack SDK named XFLARE. This SDK enables enterprise customers, telecommunication networks, and research institutions to migrate workflows onto memory-centric hardware with reduced software rewrite.
Roadmap to Production
Operating from two main R&D centers based in Sunnyvale, California, and Banqiao, South Korea, XCENA employs more than 90 engineers. The corporate senior management team has its background firmly in the chips arena. Founded in 2022 by semiconductor veterans from Samsung Electronics and SK Hynix, the world’s biggest and second-biggest memory chip suppliers.
XCENA will be leveraging the Series B runway to build a closer presence in Northern California for working with hyperscale cloud providers and infrastructure players. MX1 architecture is in the prototype stage and starting evaluation with early partners.
This long-term commercialisation approach avoids the high capital costs of establishing internal manufacturing capability. XCENA will instead take a fabless route, sourcing from current manufacturing ecospheres, with mass production of commercial-grade chips set to begin by the end of 2026 through Samsung’s foundry lines.
